1. Field of the Invention
The present invention relates to a variable word length circuit of a semiconductor memory and, more particularly, to a variable word length circuit of a semiconductor memory capable of varying a word length of data accessed serially by a shift register in a semiconductor memory in which a plurality of memory cells are arranged in row and column directions and the shift register is provided corresponding to a memory cells on a row or a column.
2. Description of the Prior Art
As conventional access methods for a semiconductor memory cell, a random access method and a serial access method have been employed. In the serial access method, a shift register is provided in a data input/output portion and a certain length of bits (hereinafter referred to as a word) is inputted and outputted serially at high speed, which is advantageous particularly in a case of transferring (inputting and outputting to a memory cell array) a data group of a certain block at high speed.
FIG. 1 is a schematic block diagram showing a semiconductor memory provided with the serial access method. Although a dynamic MOSRAM is employed as a memory cell array in the semiconductor memory shown in FIG. 1, the following description is not limited to this.
The dynamic MOSRAM comprises a memory cell array 1, a row decoder 2, a sense amplifier 3, a shift register 4, a row address buffer 50, a control signal generating circuit 60, a data-in buffer 70 and a data-out buffer 8. The memory cell array 1 comprises, though not shown in the figure, a plurality of word lines, a plurality of bit lines crossing at right angles therewith and a group of memory cells each disposed on an intersecting point of both lines. The row decoder 2 selects a corresponding word line in response to a row address signal inputted from the outside to the row address buffer 50. When any word lines is selected, data stored in a memory cell group for a selected one row appear as a signal potential on a bit line. This signal potential is detected and amplified by the sense amplifier 3.
Each memory cell group is constructed by one-transistor one-capacitor type and the sense amplifier 3 is also designed to perform refreshing operation of data of each memory cell group. In addition, the sense amplifier 3 serves as a data latch and is connected to the shift register 4 at each bit line. The data-in buffer 70 and the data-out buffer 8 are connected to the shift register 4 and the data-in buffer 70 applies the data inputted from the outside to the shift register 4. When the data is read, the data detected and amplified by the sense amplifier 3 is applied to the shift register 4, which data is serially selected in accordance with the shift operation of the shift register 4 and outputted to the data-out buffer 8.
When data is written, data to be written sent from the data-in buffer 70 is serially shifted by the shift register 4 and written to the corresponding memory cell from a bit line through the corresponding sense amplifier 3.
FIG. 2 is a waveform diagram for explaining the operation of the dynamic MOSRAM shown in FIG. 1. When an external control signal RAS applied to the control signal generating circuit 60 falls as shown in FIG. 2, the row address buffer 50 latches an external row address signal applied from the outside. In FIG. 2, row address signals for a plurality of bits are represented by "RA". When a row address signal is latched by the row address buffer 50, the row decoder 2 selects and activates the corresponding word line and the data of a plurality of bits of memory cells selected in the memory cell array 1 are amplified and latched by the sense amplifier 3.
When data is read, at every cycle in which an external control signal CAS falls as shown in FIG. 2, data is serially selected by the shift register 4 as shown in FIG. 2 and latched by the data-out buffer 8 to be then outputted. On the other hand, when data is written, at every cycle in which the external control signal CAS falls, the data which has been latched by the data-in buffer 70 is written in a memory cell.
FIGS. 3A to 3C are conceptual diagrams for explaining the operation of the shift register shown in FIG. 2. In FIGS. 3A to 3C, as one example, data of 8 bits is shown as being serially written and read. First, the first bit of the shift register 4 of 8 bits is initialized to "1" and other bits are all initialized to "0". Thereafter, as the shift register 4 is shifted by one bit at every cycle of the external control signal CAS, a bit line pair corresponding to the data "1" of the shift register 4 is successively connected to a data input/output line "I/O line" and input/output operation of data is performed. Thus, when the shift operation is performed eight times, the first bit of the shift register 4 is set to "1" again and other bits are set to "0", and thereafter, the same operation will be repeated.
In the dynamic MOSRAM shown in the above-described FIG. 1, the number of bits of one group (hereinafter referred to as a word length), which is serially accessed is the same as that of memory cells selected by one word line. In effect, however, this fact limits the application of the memory cell. Therefore, there was a disadvantage that the word length could not be changed by a simple method after production.